With the continuous increase of the integration level of semiconductor devices on a chip, the critical dimensions of the semiconductor devices have become smaller and smaller. Correspondingly, there are some challenges. For example, the surface resistances and contact resistances of doped source/drain regions of semiconductor devices have correspondingly increased. The increase of the surface resistances and the contact resistances reduces the responding speed of the semiconductor devices and generates signal delays. Thus, interconnect structures with a low resistivity have become a key factor for manufacturing the semiconductor devices with a high integration level.
To reduce the contact resistances in the doped source/drain regions of the semiconductor devices, a metal contact layer is formed on each of the doped source/drain regions. The metal contact layer is made of metal silicide. The metal silicide has a relatively low resistance, and is able to significantly reduce the contact resistances of the doped source/drain regions. The metal silicide, self-aligned metal silicide and their fabrication methods have been widely used to reduce the surface resistances and the contact resistances of the doped source/drain regions of the semiconductor devices. Reducing the surface resistances and the contact resistances is able to reduce the delay time of the resistors and the capacitors.
However, there is a need to further improve the electrical properties of semiconductor devices. The disclosed methods and semiconductor structures are directed to solve one or more problems set forth above and other problems in the art.